Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.
| Published in | Journal of Electrical and Electronic Engineering (Volume 5, Issue 6) |
| DOI | 10.11648/j.jeee.20170506.15 |
| Page(s) | 242-249 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2018. Published by Science Publishing Group |
Quaded Structure, Reliability, Cmol, Nand Gate, Nano Architecture
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APA Style
Mohammed Hadifur Rahman, Shahida Rafique, Mohammad Shafiul Alam. (2018). CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture. Journal of Electrical and Electronic Engineering, 5(6), 242-249. https://doi.org/10.11648/j.jeee.20170506.15
ACS Style
Mohammed Hadifur Rahman; Shahida Rafique; Mohammad Shafiul Alam. CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture. J. Electr. Electron. Eng. 2018, 5(6), 242-249. doi: 10.11648/j.jeee.20170506.15
AMA Style
Mohammed Hadifur Rahman, Shahida Rafique, Mohammad Shafiul Alam. CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture. J Electr Electron Eng. 2018;5(6):242-249. doi: 10.11648/j.jeee.20170506.15
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Download@article{10.11648/j.jeee.20170506.15,
author = {Mohammed Hadifur Rahman and Shahida Rafique and Mohammad Shafiul Alam},
title = {CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture},
journal = {Journal of Electrical and Electronic Engineering},
volume = {5},
number = {6},
pages = {242-249},
doi = {10.11648/j.jeee.20170506.15},
url = {https://doi.org/10.11648/j.jeee.20170506.15},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20170506.15},
abstract = {Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate.},
year = {2018}
}
TY - JOUR T1 - CMOL Based Quaded Transistor NAND Gate Building Block of Robust Nano Architecture AU - Mohammed Hadifur Rahman AU - Shahida Rafique AU - Mohammad Shafiul Alam Y1 - 2018/01/02 PY - 2018 N1 - https://doi.org/10.11648/j.jeee.20170506.15 DO - 10.11648/j.jeee.20170506.15 T2 - Journal of Electrical and Electronic Engineering JF - Journal of Electrical and Electronic Engineering JO - Journal of Electrical and Electronic Engineering SP - 242 EP - 249 PB - Science Publishing Group SN - 2329-1605 UR - https://doi.org/10.11648/j.jeee.20170506.15 AB - Nano architectures are more prone to defects. This work is aimed at finding the effectiveness of using quaded structure devices to improve the reliability of logic gates in Nano lavel. Transistor level redundancy (Quaded Structure) has been applied in a CMOS gate (NAND) design to improve the reliability. Being an universal gate, NAND gate can be the building block for nano architecture. CMOL is a hybrid architecture that combines conventional CMOS and Nano architecture together. Based on CMOL, a NAND gate design has been proposed. To study the performance of the proposed architecture, theoretical analysis has been proposed. Moreover, to evaluate the effectiveness of the quaded structured NAND (QNAND) gate, detailed simulation was carried out. Simulation results illustrates that quaded structured design achieves significantly higher defect tolerance by enhancing the reliability of the QNAND gate. VL - 5 IS - 6 ER -
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